Asynchronous Locally Synchronous Wrapper Circuits

This paper focuses on prototyping pausible and gated In this paper, after presenting an overview on the pausible clock based GALS systems on commercial FPGAs. Pausible clock clock based and gated clock based GALS systems in sections II based GLAS systems use an on-chip clock generator to generate and III, the implementation of GALS on commercial FPGA pausible clock pulses whereas gated clock based GALS systems circuits is mentioned in section IV. In section V experimental use an off-chip clock signal that is gated whenever asynchronous results are stated and fial conclusions of this research are data communication is required. These two design schemes have been examined on Viterbi error detection and correction circuit. presented i Section VI. While using on-chip pausible clocks in plausible GALS wrappers leads to a tradeoff between robustness and performance, it has been shown that both performance and robustness can be Figure 1 presents the basic configuration of a pausible clock improved by using the gated clock scheme. In addition, the area based GALS wrapper module. The Locally Synchronous (LS) overhead of gated clock based GALS Viterbi was less than the circuit performs the main desired function. The clock generator area overhead of pausible clock based GALS Viterbi. generates clock pulses and asynchronous port controllers intervene between LS and asynchronous environment.